XCV400E-6PQG240C

Xilinx,Inc.

Xilinx,Inc. XCV400E-6PQG240C
  • ECCN
    EAR99
  • ECCN Governance
    EAR
  • HTS Code
    8542.39.00.01
  • SB Code
    8542.39.00.00
  • Width
    32 mm
  • Length
    32 mm
  • Technology
    CMOS
  • JESD-30 Code
    S-PQFP-G240
  • Organization
    2400 CLBS, 129600 GATES
  • Package Code
    FQFP
  • JESD-609 Code
    e3
  • Package Shape
    SQUARE
  • Package Style
    FLATPACK, FINE PITCH Meter
  • Surface Mount
    YES
  • Terminal Form
    GULL WING
  • Number of CLBs
    2400
  • Terminal Pitch
    0.5 mm
  • Terminal Finish
    Matte Tin (Sn)
  • Number of Inputs
    158
  • Number of Outputs
    158
  • Seated Height-Max
    4.1 mm
  • Temperature Grade
    OTHER
  • Terminal Position
    QUAD
  • Supply Voltage-Max
    1.89 V
  • Supply Voltage-Min
    1.71 V
  • Supply Voltage-Nom
    1.8 V
  • Clock Frequency-Max
    357 MHz
  • Number of Terminals
    240
  • Qualification Status
    Not Qualified
  • Number of Logic Cells
    10800
  • Package Body Material
    PLASTIC/EPOXY
  • Programmable Logic Type
    FIELD PROGRAMMABLE GATE ARRAY
  • Package Equivalence Code
    QFP240,1.3SQ,20
  • Operating Temperature-Max
    85 Cel
  • Operating Temperature-Min
    0 Cel
  • Moisture Sensitivity Level
    3
  • Number of Equivalent Gates
    129600
  • Peak Reflow Temperature (Cel)
    245
  • Combinatorial Delay of a CLB-Max
    0.47 ns
  • Time@Peak Reflow Temperature-Max (s)
    30

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