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XCV400E-6BGG560C

Xilinx,Inc.

Xilinx,Inc. XCV400E-6BGG560C
  • ECCN
    3A991.D
  • ECCN Governance
    EAR
  • HTS Code
    8542.39.00.01
  • SB Code
    8542.39.00.00
  • Width
    42.5 mm
  • Length
    42.5 mm
  • Technology
    CMOS
  • JESD-30 Code
    S-PBGA-B560
  • Organization
    2400 CLBS, 129600 GATES
  • Package Code
    LBGA
  • JESD-609 Code
    e1
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY, LOW PROFILE Meter
  • Surface Mount
    YES
  • Terminal Form
    BALL
  • Number of CLBs
    2400
  • Terminal Pitch
    1.27 mm
  • Terminal Finish
    Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
  • Number of Inputs
    404
  • Number of Outputs
    404
  • Seated Height-Max
    1.7 mm
  • Temperature Grade
    OTHER
  • Terminal Position
    BOTTOM
  • Supply Voltage-Max
    1.89 V
  • Supply Voltage-Min
    1.71 V
  • Supply Voltage-Nom
    1.8 V
  • Clock Frequency-Max
    357 MHz
  • Number of Terminals
    560
  • Qualification Status
    Not Qualified
  • Number of Logic Cells
    10800
  • Package Body Material
    PLASTIC/EPOXY
  • Programmable Logic Type
    FIELD PROGRAMMABLE GATE ARRAY
  • Package Equivalence Code
    BGA560,33X33,50
  • Operating Temperature-Max
    85 Cel
  • Operating Temperature-Min
    0 Cel
  • Moisture Sensitivity Level
    3
  • Number of Equivalent Gates
    129600
  • Peak Reflow Temperature (Cel)
    260
  • Combinatorial Delay of a CLB-Max
    0.47 ns
  • Time@Peak Reflow Temperature-Max (s)
    30

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XCV400E-6BGG560C
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XCV400E-6BGG560C