ProductsManufacturers
Events
Send an RFQBOM Tool

XC73144-12PG184M

Xilinx,Inc.

Xilinx,Inc. XC73144-12PG184M
  • ECCN
    3A001.a.2.c
  • ECCN Governance
    EAR
  • HTS Code
    8542.31.00.55
  • SB Code
    8542.31.00.55
  • Technology
    CMOS
  • JESD-30 Code
    S-CPGA-P184
  • Organization
    0 DEDICATED INPUTS, 120 I/O
  • Package Code
    PGA
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY Meter
  • Surface Mount
    NO
  • Terminal Form
    PIN/PEG
  • Output Function
    MACROCELL
  • DLA Qualification
    Not Qualified
  • Temperature Grade
    MILITARY
  • Terminal Position
    PERPENDICULAR
  • Additional Feature
    144 MACROCELLS WITH PROGRAMMABLE I/O ARCHITECTURE
  • Number of I/O Lines
    120
  • Number of Terminals
    184
  • Package Body Material
    CERAMIC, METAL-SEALED COFIRED
  • Supply Voltage-Max (V)
    5.5
  • Supply Voltage-Min (V)
    4.5
  • Supply Voltage-Nom (V)
    5
  • Programmable Logic Type
    UV PLD
  • Number of Dedicated Inputs
    0
  • Operating Temperature-Max (Cel)
    125
  • Operating Temperature-Min (Cel)
    -55

0 suppliers available to buy or to bid for XC73144-12PG184M

Send an RFQ

Your RFQ will be directly sent to our expert: Pari

Send an RFQ
XC73144-12PG184M
Send an RFQ
XC73144-12PG184M