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XC5202-6VQG64I

Xilinx,Inc.

Xilinx,Inc. XC5202-6VQG64I
  • HTS Code
    8542.39.00.01
  • SB Code
    8542.31.00.60
  • Technology
    CMOS
  • Width (mm)
    10
  • Length (mm)
    10
  • JESD-30 Code
    S-PQFP-G64
  • Organization
    64 CLBS, 2000 GATES
  • Package Code
    TFQFP
  • Package Shape
    SQUARE
  • Package Style
    FLATPACK, THIN PROFILE, FINE PITCH Meter
  • Surface Mount
    YES
  • Terminal Form
    GULL WING
  • J-STD-609 Code
    e3
  • Number of CLBs
    64
  • Terminal Finish
    MATTE TIN
  • Number of Inputs
    52
  • DLA Qualification
    Not Qualified
  • Number of Outputs
    52
  • Terminal Position
    QUAD
  • Additional Feature
    MAX AVAILABLE 3000 LOGIC GATES
  • Number of Terminals
    64
  • Terminal Pitch (mm)
    0.5
  • Package Body Material
    PLASTIC/EPOXY
  • Seated Height-Max (mm)
    1.2
  • Supply Voltage-Max (V)
    5.5
  • Supply Voltage-Min (V)
    4.5
  • Supply Voltage-Nom (V)
    5
  • Programmable Logic Type
    FIELD PROGRAMMABLE GATE ARRAY
  • Package Equivalence Code
    TQFP64,.47SQ
  • Clock Frequency-Max (MHz)
    83
  • Moisture Sensitivity Level
    3
  • Number of Equivalent Gates
    2000
  • Peak Reflow Temperature (Cel)
    260
  • Operating Temperature-Max (Cel)
    100
  • Operating Temperature-Min (Cel)
    -40
  • Time@Peak Reflow Temperature-Max (s)
    30
  • Combinatorial Delay of a CLB-Max (ns)
    5.6

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XC5202-6VQG64I