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XC3S500E-5FGG320CS1

Xilinx,Inc.

Xilinx,Inc. XC3S500E-5FGG320CS1
  • HTS Code
    8542.39.00.01
  • SB Code
    8542.31.00.60
  • Technology
    CMOS
  • JESD-30 Code
    S-PBGA-B320
  • Package Code
    BGA
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY Meter
  • Surface Mount
    YES
  • Terminal Form
    BALL
  • J-STD-609 Code
    e1
  • Terminal Finish
    TIN SILVER COPPER
  • Number of Inputs
    232
  • DLA Qualification
    Not Qualified
  • Number of Outputs
    176
  • Terminal Position
    BOTTOM
  • Number of Terminals
    320
  • Terminal Pitch (mm)
    1
  • Number of Logic Cells
    10476
  • Package Body Material
    PLASTIC/EPOXY
  • Programmable Logic Type
    FIELD PROGRAMMABLE GATE ARRAY
  • Package Equivalence Code
    BGA320,18X18,40
  • Clock Frequency-Max (MHz)
    657
  • Moisture Sensitivity Level
    3
  • Peak Reflow Temperature (Cel)
    260
  • Time@Peak Reflow Temperature-Max (s)
    30

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XC3S500E-5FGG320CS1