XC3064-50PG132B

Xilinx,Inc.

Xilinx,Inc. XC3064-50PG132B
  • ECCN
    3A001.a.2.c
  • ECCN Governance
    EAR
  • HTS Code
    8542.31.00.60
  • SB Code
    8542.31.00.60
  • Technology
    CMOS
  • JESD-30 Code
    S-XPGA-P132
  • Organization
    224 CLBS, 4000 GATES
  • Package Code
    PGA
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY Meter
  • Surface Mount
    NO
  • Terminal Form
    PIN/PEG
  • Number of Inputs
    110
  • DLA Qualification
    Not Qualified
  • Number of Outputs
    110
  • Temperature Grade
    MILITARY
  • Terminal Position
    PERPENDICULAR
  • Number of Terminals
    132
  • Terminal Pitch (mm)
    2.54
  • Number of Logic Cells
    224
  • Package Body Material
    CERAMIC
  • Supply Voltage-Max (V)
    5.5
  • Supply Voltage-Min (V)
    4.5
  • Supply Voltage-Nom (V)
    5
  • Programmable Logic Type
    FIELD PROGRAMMABLE GATE ARRAY
  • Package Equivalence Code
    PGA132,14X14
  • Clock Frequency-Max (MHz)
    50
  • Number of Equivalent Gates
    4000
  • Operating Temperature-Max (Cel)
    125
  • Operating Temperature-Min (Cel)
    -55
  • Screening Level / Reference Standard
    38535Q/M;38534H;883B
  • Combinatorial Delay of a CLB-Max (ns)
    14

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