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XC2VP2-7FGG256I

Xilinx,Inc.

Xilinx,Inc. XC2VP2-7FGG256I
  • HTS Code
    8542.39.00.01
  • SB Code
    8542.31.00.60
  • Technology
    CMOS
  • Width (mm)
    17
  • Length (mm)
    17
  • JESD-30 Code
    S-PBGA-B256
  • Organization
    352 CLBS
  • Package Code
    BGA
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY Meter
  • Surface Mount
    YES
  • Terminal Form
    BALL
  • J-STD-609 Code
    e1
  • Number of CLBs
    352
  • Terminal Finish
    TIN SILVER COPPER
  • DLA Qualification
    Not Qualified
  • Terminal Position
    BOTTOM
  • Number of Terminals
    256
  • Terminal Pitch (mm)
    1
  • Package Body Material
    PLASTIC/EPOXY
  • Seated Height-Max (mm)
    2
  • Supply Voltage-Max (V)
    1.575
  • Supply Voltage-Min (V)
    1.425
  • Supply Voltage-Nom (V)
    1.5
  • Programmable Logic Type
    FIELD PROGRAMMABLE GATE ARRAY
  • Package Equivalence Code
    BGA256,16X16,40
  • Clock Frequency-Max (MHz)
    1350
  • Moisture Sensitivity Level
    3
  • Combinatorial Delay of a CLB-Max (ns)
    0.28

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XC2VP2-7FGG256I