XC2S100E-6PQG208C by Xilinx,Inc. | Sourcengine

Xilinx,Inc. XC2S100E-6PQG208C

Lifecycle status
EOL
Description
FPGA - Field Programmable Gate Array
Category
Semiconductors Programmable Logic ICs Field Programmable Gate Arrays FIELD PROGRAMMABLE GATE ARRAY

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Width
28 mm
Length
28 mm
Technology
CMOS
JESD-30 Code
S-PQFP-G208
Organization
600 CLBS, 37000 GATES
Package Code
FQFP
JESD-609 Code
e3
Package Shape
SQUARE
Package Style
FLATPACK, FINE PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
Number of CLBs
600
Terminal Pitch
0.5 mm
Terminal Finish
Matte Tin (Sn)
Number of Inputs
202
Number of Outputs
202
Seated Height-Max
4.1 mm
Temperature Grade
OTHER
Terminal Position
QUAD
Additional Feature
MAXIMUM USABLE GATES = 100000
Supply Voltage-Max
1.89 V
Supply Voltage-Min
1.71 V
Supply Voltage-Nom
1.8 V
Clock Frequency-Max
357 MHz
Number of Terminals
208
Qualification Status
Not Qualified
Number of Logic Cells
2700
Package Body Material
PLASTIC/EPOXY
Programmable Logic Type
FIELD PROGRAMMABLE GATE ARRAY
Package Equivalence Code
QFP208,1.2SQ,20
Operating Temperature-Max
85 Cel
Operating Temperature-Min
0 Cel
Moisture Sensitivity Level
3
Number of Equivalent Gates
37000
Peak Reflow Temperature (Cel)
245
Combinatorial Delay of a CLB-Max
0.47 ns
Time@Peak Reflow Temperature-Max (s)
30