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XC2018-50PG84M

Xilinx,Inc.

Xilinx,Inc. XC2018-50PG84M
  • ECCN
    3A001.a.2.c
  • ECCN Governance
    EAR
  • HTS Code
    8542.31.00.60
  • SB Code
    8542.31.00.60
  • Technology
    CMOS
  • Width (mm)
    27.94
  • Length (mm)
    27.94
  • JESD-30 Code
    S-CPGA-P84
  • Organization
    100 CLBS, 1000 GATES
  • Package Code
    PGA
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY Meter
  • Surface Mount
    NO
  • Terminal Form
    PIN/PEG
  • Number of CLBs
    100
  • Number of Inputs
    74
  • DLA Qualification
    Not Qualified
  • Number of Outputs
    74
  • Temperature Grade
    MILITARY
  • Terminal Position
    PERPENDICULAR
  • Additional Feature
    174 FLIP-FLOPS; TYP. GATES = 1000-1500
  • Number of Terminals
    84
  • Terminal Pitch (mm)
    2.54
  • Number of Logic Cells
    100
  • Package Body Material
    CERAMIC, METAL-SEALED COFIRED
  • Seated Height-Max (mm)
    4.318
  • Supply Voltage-Max (V)
    5.5
  • Supply Voltage-Min (V)
    4.5
  • Supply Voltage-Nom (V)
    5
  • Programmable Logic Type
    FIELD PROGRAMMABLE GATE ARRAY
  • Package Equivalence Code
    PGA84M,11X11
  • Clock Frequency-Max (MHz)
    50
  • Number of Equivalent Gates
    1000
  • Peak Reflow Temperature (Cel)
    NOT SPECIFIED
  • Operating Temperature-Max (Cel)
    125
  • Operating Temperature-Min (Cel)
    -55
  • Time@Peak Reflow Temperature-Max (s)
    NOT SPECIFIED
  • Combinatorial Delay of a CLB-Max (ns)
    15

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XC2018-50PG84M