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XA3S50-4VQ100I

Xilinx,Inc.

Xilinx,Inc. XA3S50-4VQ100I
  • HTS Code
    8542.39.00.01
  • SB Code
    8542.31.00.60
  • Width (mm)
    14
  • Length (mm)
    14
  • JESD-30 Code
    S-PQFP-G100
  • Organization
    192 CLBS, 50000 GATES
  • Package Code
    TFQFP
  • Package Shape
    SQUARE
  • Package Style
    FLATPACK, THIN PROFILE, FINE PITCH Meter
  • Surface Mount
    YES
  • Terminal Form
    GULL WING
  • J-STD-609 Code
    e0
  • Number of CLBs
    192
  • Terminal Finish
    TIN LEAD
  • Number of Inputs
    124
  • DLA Qualification
    Not Qualified
  • Number of Outputs
    124
  • Terminal Position
    QUAD
  • Number of Terminals
    100
  • Terminal Pitch (mm)
    0.5
  • Number of Logic Cells
    1728
  • Package Body Material
    PLASTIC/EPOXY
  • Seated Height-Max (mm)
    1.2
  • Supply Voltage-Max (V)
    1.26
  • Supply Voltage-Min (V)
    1.14
  • Supply Voltage-Nom (V)
    1.2
  • Programmable Logic Type
    FIELD PROGRAMMABLE GATE ARRAY
  • Package Equivalence Code
    TQFP100,.63SQ
  • Clock Frequency-Max (MHz)
    125
  • Moisture Sensitivity Level
    3
  • Number of Equivalent Gates
    50000
  • Peak Reflow Temperature (Cel)
    240
  • Screening Level / Reference Standard
    AEC-Q100
  • Time@Peak Reflow Temperature-Max (s)
    30

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XA3S50-4VQ100I