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WEDSP3261-SQ.PGA

AT & T MICROELECTRONICS

AT & T MICROELECTRONICS WEDSP3261-SQ.PGA
  • HTS Code
    8542.31.00.01
  • SB Code
    8542.31.00.35
  • Format
    FLOATING POINT
  • Bit Size
    32
  • Technology
    NMOS
  • RAM (words)
    512
  • JESD-30 Code
    S-CPGA-P104
  • Package Code
    PGA
  • Boundary Scan
    NO
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY Meter
  • Surface Mount
    NO
  • Terminal Form
    PIN/PEG
  • Barrel Shifter
    NO
  • Low Power Mode
    NO
  • Integrated Cache
    NO
  • Number of Timers
    0
  • Address Bus Width
    14
  • DLA Qualification
    Not Qualified
  • Temperature Grade
    OTHER
  • Terminal Position
    PERPENDICULAR
  • Additional Feature
    2 EXECUTION UNITS
  • Number of Terminals
    104
  • Program Memory Type
    MROM
  • Number of Serial I/Os
    1
  • Package Body Material
    CERAMIC, METAL-SEALED COFIRED
  • Number of DMA Channels
    0
  • On Chip Data RAM Width
    32
  • Supply Voltage-Max (V)
    5.5
  • Supply Voltage-Min (V)
    4.5
  • Supply Voltage-Nom (V)
    5
  • External Data Bus Width
    32
  • Supply Current-Max (mA)
    600
  • Clock Frequency-Max (MHz)
    16
  • Internal Bus Architecture
    SINGLE
  • Program Memory Width (bits)
    32
  • uPs/uCs/Peripheral ICs Type
    DIGITAL SIGNAL PROCESSOR, OTHER
  • Number of External Interrupts
    1
  • Operating Temperature-Max (Cel)
    115
  • Operating Temperature-Min (Cel)
    0

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WEDSP3261-SQ.PGA