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MR80C31/B

MATRA MHS

MATRA MHS MR80C31/B
  • ECCN
    3A001.a.2.c
  • ECCN Governance
    EAR
  • HTS Code
    8542.31.00.15
  • SB Code
    8542.31.00.15
  • Format
    FIXED POINT
  • Bit Size
    8
  • Technology
    CMOS
  • RAM (words)
    128
  • Speed (MHz)
    12
  • ADC Channels
    NO
  • DAC Channels
    NO
  • DMA Channels
    NO
  • JESD-30 Code
    S-CQCC-N44
  • PWM Channels
    NO
  • Package Code
    QCCN
  • Boundary Scan
    NO
  • Package Shape
    SQUARE
  • Package Style
    CHIP CARRIER Meter
  • Surface Mount
    YES
  • Terminal Form
    NO LEAD
  • Low Power Mode
    YES
  • Integrated Cache
    NO
  • Number of Timers
    2
  • Address Bus Width
    16
  • DLA Qualification
    Not Qualified
  • Temperature Grade
    MILITARY
  • Terminal Position
    QUAD
  • Additional Feature
    BOOLEAN PROCESSOR
  • Number of I/O Lines
    32
  • Number of Terminals
    44
  • Program Memory Type
    ROM LESS
  • Terminal Pitch (mm)
    1.27
  • Number of Serial I/Os
    1
  • Package Body Material
    CERAMIC, METAL-SEALED COFIRED
  • Number of DMA Channels
    0
  • On Chip Data RAM Width
    8
  • Supply Voltage-Max (V)
    5.5
  • Supply Voltage-Min (V)
    4.5
  • Supply Voltage-Nom (V)
    5
  • External Data Bus Width
    8
  • Supply Current-Max (mA)
    21
  • Clock Frequency-Max (MHz)
    12
  • Program Memory Size (words)
    0
  • uPs/uCs/Peripheral ICs Type
    MICROCONTROLLER
  • Number of External Interrupts
    2
  • Operating Temperature-Max (Cel)
    125
  • Operating Temperature-Min (Cel)
    -55

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MR80C31/B
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MR80C31/B