MK74ZD133FLFT by INTEGRATED CIRCUIT SYSTEMS INC | Sourcengine

INTEGRATED CIRCUIT SYSTEMS INC MK74ZD133FLFT

Lifecycle status
Transferred
Description
PLL Based Clock Driver, ZD Series, 32 True Output(s), 0 Inverted Output(s), CMOS, PDSO56
Category
Semiconductors Logic ICs Clock Drivers PLL BASED CLOCK DRIVER

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
ZD
Technology
CMOS
Width (mm)
7.5
Length (mm)
18.415
JESD-30 Code
R-PDSO-G56
Package Code
SSOP
Logic IC Type
PLL BASED CLOCK DRIVER
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e3
fmax-Min (MHz)
80
Terminal Finish
MATTE TIN
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
DUAL
Input Conditioning
STANDARD
Number of Functions
1
Number of Terminals
56
Terminal Pitch (mm)
0.635
Package Body Material
PLASTIC/EPOXY
Number of True Outputs
32
Output Characteristics
3-STATE
Seated Height-Max (mm)
2.794
Supply Voltage-Max (V)
3.45
Supply Voltage-Min (V)
3.15
Supply Voltage-Nom (V)
3.3
Number of Inverted Outputs
0
Peak Reflow Temperature (Cel)
NOT SPECIFIED
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0
Same Edge Clock Skew Delay-Max (ns)
0.2
Time@Peak Reflow Temperature-Max (s)
NOT SPECIFIED