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MC68606RC12C

Motorola,Inc.

Motorola,Inc. MC68606RC12C
  • HTS Code
    8542.31.00.01
  • SB Code
    8542.31.00.30
  • Technology
    CMOS
  • RAM (words)
    0
  • JESD-30 Code
    S-CPGA-P84
  • Package Code
    PGA
  • Boundary Scan
    NO
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY Meter
  • Surface Mount
    NO
  • Terminal Form
    PIN/PEG
  • Low Power Mode
    NO
  • Address Bus Width
    24
  • Bus Compatibility
    M68000; IAPX 86
  • DLA Qualification
    Not Qualified
  • Terminal Position
    PERPENDICULAR
  • Number of I/O Lines
    0
  • Number of Terminals
    84
  • Terminal Pitch (mm)
    2.54
  • Number of Serial I/Os
    1
  • Package Body Material
    CERAMIC, METAL-SEALED COFIRED
  • Communication Standard
    SYNC, HDLC; LAPD
  • Number of DMA Channels
    1
  • On Chip Data RAM Width
    0
  • Seated Height-Max (mm)
    2.66
  • Supply Voltage-Max (V)
    5.25
  • Supply Voltage-Min (V)
    4.75
  • Supply Voltage-Nom (V)
    5
  • External Data Bus Width
    16
  • Clock Frequency-Max (MHz)
    12.5
  • uPs/uCs/Peripheral ICs Type
    SERIAL IO/COMMUNICATION CONTROLLER, MULTI PROTOCOL
  • Data Encoding/Decoding Method
    NRZ
  • Data Transfer Rate-Max (MBps)
    0.256

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MC68606RC12C
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MC68606RC12C