M312L5128AU0-A2
Samsung Semiconductor, Inc.
- Lifecycle statusDiscontinued
- RoHSRoHS compliant
- DescriptionCache DRAM Module, 512MX72, 0.75ns, CMOS, PDMA184
- Category
- ECCNEAR99
- ECCN GovernanceEAR
- HTS Code8542.32.00.36
- SB Code8542.32.00.23
- I/O TypeCOMMON
- TechnologyCMOS
- JESD-30 CodeR-PDMA-N184
- Memory Width72
- Organization512MX72
- Package CodeDIMM
- JESD-609 Codee3
- Package ShapeRECTANGULAR
- Package StyleMICROELECTRONIC ASSEMBLY Meter
- Surface MountNO
- Terminal FormNO LEAD
- Memory Density38654705664 bit
- Memory IC TypeCACHE DRAM MODULE
- Refresh Cycles8192
- Terminal Pitch1.27 mm
- Access Time-Max0.75 ns
- Number of Words536870912 words
- Terminal FinishMATTE TIN
- Temperature GradeCOMMERCIAL
- Terminal PositionDUAL
- Supply Current-Max8740 mA
- Number of Terminals184
- Standby Current-Max1.12 Amp
- Number of Words Code512M
- Qualification StatusNot Qualified
- Package Body MaterialPLASTIC/EPOXY
- Output Characteristics3-STATE
- Package Equivalence CodeDIMM184
- Operating Temperature-Max70 Cel
- Operating Temperature-Min0 Cel
- Supply Voltage-Nom (Vsup)2.5 V
- Clock Frequency-Max (fCLK)133 MHz
- Moisture Sensitivity Level1
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M312L5128AU0-A2