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IDT7MP6048S17M

Integrated Device Technology, Inc.

Integrated Device Technology, Inc. IDT7MP6048S17M
  • ECCN
    3A991.b.2.a
  • ECCN Governance
    EAR
  • HTS Code
    8542.32.00.41
  • SB Code
    8542.32.00.40
  • Technology
    CMOS
  • JESD-30 Code
    R-XSMA-N80
  • Memory Width
    36
  • Package Shape
    RECTANGULAR
  • Package Style
    MICROELECTRONIC ASSEMBLY Meter
  • Surface Mount
    NO
  • Terminal Form
    NO LEAD
  • J-STD-609 Code
    e0
  • Memory IC Type
    CACHE SRAM MODULE
  • Operating Mode
    ASYNCHRONOUS
  • Parallel/Serial
    PARALLEL
  • Terminal Finish
    TIN LEAD
  • DLA Qualification
    Not Qualified
  • Temperature Grade
    COMMERCIAL
  • Terminal Position
    SINGLE
  • Additional Feature
    CACHE TAG CONFIGURABLE AS 64K X 8
  • Memory Organization
    64KX36
  • Number of Functions
    1
  • Number of Terminals
    80
  • Access Time-Max (ns)
    17
  • Number of Words Code
    64K
  • Memory Density (bits)
    2359296
  • Package Body Material
    UNSPECIFIED
  • Supply Voltage-Max (V)
    5.5
  • Supply Voltage-Min (V)
    4.5
  • Supply Voltage-Nom (V)
    5
  • Number of Words (words)
    65536
  • Operating Temperature-Max (Cel)
    70
  • Operating Temperature-Min (Cel)
    0

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IDT7MP6048S17M