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HSP45102PC-50

HARRIS SEMICONDUCTOR

HSP45102PC-50 Datasheet
HARRIS SEMICONDUCTOR HSP45102PC-50
  • ECCN
    3A991.a.2
  • ECCN Governance
    EAR
  • HTS Code
    8542.39.00.60
  • SB Code
    8542.39.00.60
  • Technology
    CMOS
  • JESD-30 Code
    R-PDIP-T28
  • Package Code
    DIP
  • Boundary Scan
    NO
  • Package Shape
    RECTANGULAR
  • Package Style
    IN-LINE Meter
  • Surface Mount
    NO
  • Terminal Form
    THROUGH-HOLE
  • Low Power Mode
    YES
  • DLA Qualification
    Not Qualified
  • Temperature Grade
    COMMERCIAL
  • Terminal Position
    DUAL
  • Number of Terminals
    28
  • Output Data Bus Width
    12
  • Package Body Material
    PLASTIC/EPOXY
  • Supply Voltage-Max (V)
    5.25
  • Supply Voltage-Min (V)
    4.75
  • Supply Voltage-Nom (V)
    5
  • External Data Bus Width
    0
  • Clock Frequency-Max (MHz)
    50
  • uPs/uCs/Peripheral ICs Type
    DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR
  • Operating Temperature-Max (Cel)
    70
  • Operating Temperature-Min (Cel)
    0

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HSP45102PC-50
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HSP45102PC-50