HD63450-12
Hitachi, Ltd.
- Lifecycle statusDiscontinued
- DescriptionDMA Controller, 4 Channel(s), 12.5MHz, CMOS, CDIP64
- Category
- HTS Code8542.31.00.01
- SB Code8542.31.00.30
- TechnologyCMOS
- Width (mm)22.86
- Length (mm)81.28
- JESD-30 CodeR-CDIP-T64
- Package CodeDIP
- Package ShapeRECTANGULAR
- Package StyleIN-LINE Meter
- Surface MountNO
- Terminal FormTHROUGH-HOLE
- J-STD-609 Codee0
- Terminal FinishTIN LEAD
- Address Bus Width24
- Bus Compatibility68000
- DLA QualificationNot Qualified
- Temperature GradeCOMMERCIAL
- Terminal PositionDUAL
- Additional FeatureFIXED & ROTATIONAL PRIORITY INTERRUPT MODES; DATA TRANSFER RATE [MBYTES/SEC.] = 6.25
- Number of Terminals64
- Terminal Pitch (mm)2.54
- Package Body MaterialCERAMIC, METAL-SEALED COFIRED
- Number of DMA Channels4
- Seated Height-Max (mm)5.08
- Supply Voltage-Max (V)5.5
- Supply Voltage-Min (V)4.5
- Supply Voltage-Nom (V)5
- External Data Bus Width16
- Package Equivalence CodeDIP64,.9
- Clock Frequency-Max (MHz)12.5
- uPs/uCs/Peripheral ICs TypeDMA CONTROLLER
- Operating Temperature-Max (Cel)70
- Operating Temperature-Min (Cel)0
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HD63450-12