EPM7256AEFC100-5
ALTERA CORP
- Lifecycle statusTransferred
- DescriptionEE PLD, 5.5ns, 256-Cell, CMOS, PBGA100
- Category
- HTS Code8542.39.00.01
- SB Code8542.31.00.55
- JTAG BSTYES
- TechnologyCMOS
- Width (mm)11
- Length (mm)11
- JESD-30 CodeS-PBGA-B100
- Organization0 DEDICATED INPUTS, 84 I/O
- Package CodeLBGA
- Package ShapeSQUARE
- Package StyleGRID ARRAY, LOW PROFILE Meter
- Surface MountYES
- Terminal FormBALL
- J-STD-609 Codee0
- Output FunctionMACROCELL
- Terminal FinishTIN LEAD
- DLA QualificationNot Qualified
- Temperature GradeCOMMERCIAL
- Terminal PositionBOTTOM
- Additional FeatureYES
- Number of I/O Lines84
- Number of Terminals100
- Terminal Pitch (mm)1
- Number of Macro Cells256
- Package Body MaterialPLASTIC/EPOXY
- In-System ProgrammableYES
- Propagation Delay (ns)5.5
- Seated Height-Max (mm)1.7
- Supply Voltage-Max (V)3.6
- Supply Voltage-Min (V)3
- Supply Voltage-Nom (V)3.3
- Programmable Logic TypeEE PLD
- Package Equivalence CodeBGA100,10X10,40
- Clock Frequency-Max (MHz)172.4
- Moisture Sensitivity Level3
- Number of Dedicated Inputs0
- Peak Reflow Temperature (Cel)235
- Operating Temperature-Max (Cel)70
- Operating Temperature-Min (Cel)0
- Time@Peak Reflow Temperature-Max (s)20
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EPM7256AEFC100-5