EPM5128AGC-15
ALTERA CORP
- Lifecycle statusDiscontinued
- DescriptionUV PLD, 25ns, 128-Cell, CMOS, CPGA68
- Category
- HTS Code8542.39.00.01
- SB Code8542.31.00.55
- JTAG BSTNO
- TechnologyCMOS
- Width (mm)27.94
- Length (mm)27.94
- JESD-30 CodeS-CPGA-P68
- Organization7 DEDICATED INPUTS, 52 I/O
- Package CodeWPGA
- Package ShapeSQUARE
- Package StyleGRID ARRAY, WINDOW Meter
- Surface MountNO
- Terminal FormPIN/PEG
- J-STD-609 Codee0
- Output FunctionMACROCELL
- Terminal FinishTIN LEAD
- Number of Inputs60
- DLA QualificationNot Qualified
- Number of Outputs52
- Temperature GradeCOMMERCIAL
- Terminal PositionPERPENDICULAR
- Additional FeatureLABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
- Number of I/O Lines52
- Number of Terminals68
- Terminal Pitch (mm)2.54
- Number of Macro Cells128
- Package Body MaterialCERAMIC, METAL-SEALED COFIRED
- In-System ProgrammableNO
- Propagation Delay (ns)25
- Seated Height-Max (mm)3.81
- Supply Voltage-Max (V)5.25
- Supply Voltage-Min (V)4.75
- Supply Voltage-Nom (V)5
- Programmable Logic TypeUV PLD
- Package Equivalence CodePGA68,11X11
- Clock Frequency-Max (MHz)83.3
- Moisture Sensitivity Level1
- Number of Dedicated Inputs7
- Peak Reflow Temperature (Cel)220
- Operating Temperature-Max (Cel)70
- Operating Temperature-Min (Cel)0
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EPM5128AGC-15