EP20K300EFI672-2 by Intel Corporation | Sourcengine

Intel Corporation EP20K300EFI672-2

Lifecycle status
Active-Unconfirmed
REACH
REACH compliant
Description
Loadable PLD, CMOS, PBGA672
Category
Semiconductors Programmable Logic ICs Programmable Logic Devices LOADABLE PLD

ECCN
3A991.d
ECCN Governance
EAR
HTS Code
8542.31.00.55
SB Code
8542.31.00.55

JTAG BST
YES
Technology
CMOS
Width (mm)
27
Length (mm)
27
Architecture
PLA-TYPE
JESD-30 Code
S-PBGA-B672
Organization
4 DEDICATED INPUTS, 408 I/O
Package Code
BGA
Package Shape
SQUARE
Package Style
GRID ARRAY Meter
Surface Mount
YES
Terminal Form
BALL
Output Function
MACROCELL
Number of Inputs
404
DLA Qualification
Not Qualified
Number of Outputs
400
Terminal Position
BOTTOM
Number of I/O Lines
408
Number of Terminals
672
Terminal Pitch (mm)
1
Number of Macro Cells
1152
Package Body Material
PLASTIC/EPOXY
In-System Programmable
YES
Propagation Delay (ns)
2.29
Seated Height-Max (mm)
2.6
Supply Voltage-Max (V)
1.89
Supply Voltage-Min (V)
1.71
Supply Voltage-Nom (V)
1.8
Number of Product Terms
32
Programmable Logic Type
LOADABLE PLD
Package Equivalence Code
BGA672,26X26,40
Clock Frequency-Max (MHz)
1818
Number of Dedicated Inputs
4
Operating Temperature-Max (Cel)
100
Operating Temperature-Min (Cel)
-40