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EP20K100FI324-1

ALTERA CORP

ALTERA CORP EP20K100FI324-1
  • ECCN
    3A991.d
  • ECCN Governance
    EAR
  • HTS Code
    8542.31.00.55
  • SB Code
    8542.31.00.55
  • JTAG BST
    YES
  • Technology
    CMOS
  • Width (mm)
    19
  • Length (mm)
    19
  • Architecture
    PLA-TYPE
  • JESD-30 Code
    S-PBGA-B324
  • Organization
    4 DEDICATED INPUTS, 246 I/O
  • Package Code
    BGA
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY Meter
  • Surface Mount
    YES
  • Terminal Form
    BALL
  • J-STD-609 Code
    e0
  • Output Function
    MACROCELL
  • Terminal Finish
    TIN LEAD
  • Number of Inputs
    246
  • DLA Qualification
    Not Qualified
  • Number of Outputs
    246
  • Terminal Position
    BOTTOM
  • Number of I/O Lines
    246
  • Number of Terminals
    324
  • Terminal Pitch (mm)
    1
  • Number of Logic Cells
    4160
  • Package Body Material
    PLASTIC/EPOXY
  • In-System Programmable
    YES
  • Propagation Delay (ns)
    2.5
  • Seated Height-Max (mm)
    2.1
  • Supply Voltage-Max (V)
    2.625
  • Supply Voltage-Min (V)
    2.375
  • Supply Voltage-Nom (V)
    2.5
  • Programmable Logic Type
    LOADABLE PLD
  • Package Equivalence Code
    BGA324(UNSPEC)
  • Clock Frequency-Max (MHz)
    1250
  • Moisture Sensitivity Level
    3
  • Number of Dedicated Inputs
    4
  • Peak Reflow Temperature (Cel)
    220
  • Operating Temperature-Max (Cel)
    100
  • Operating Temperature-Min (Cel)
    -40

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EP20K100FI324-1
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EP20K100FI324-1