EP20K100FC324-1X by ALTERA CORP | Sourcengine

ALTERA CORP EP20K100FC324-1X

Lifecycle status
Transferred
Description
Loadable PLD, 2.5ns, CMOS, PBGA324
Category
Semiconductors Programmable Logic ICs Programmable Logic Devices LOADABLE PLD

ECCN
3A991.d
ECCN Governance
EAR
HTS Code
8542.31.00.55
SB Code
8542.31.00.55

JTAG BST
YES
Technology
CMOS
Width (mm)
19
Length (mm)
19
Architecture
PLA-TYPE
JESD-30 Code
S-PBGA-B324
Organization
4 DEDICATED INPUTS, 252 I/O
Package Code
BGA
Package Shape
SQUARE
Package Style
GRID ARRAY Meter
Surface Mount
YES
Terminal Form
BALL
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
Number of Inputs
246
DLA Qualification
Not Qualified
Number of Outputs
246
Temperature Grade
OTHER
Terminal Position
BOTTOM
Number of I/O Lines
252
Number of Terminals
324
Terminal Pitch (mm)
1
Number of Logic Cells
4160
Package Body Material
PLASTIC/EPOXY
In-System Programmable
YES
Propagation Delay (ns)
2.5
Seated Height-Max (mm)
3.5
Supply Voltage-Max (V)
2.625
Supply Voltage-Min (V)
2.375
Supply Voltage-Nom (V)
2.5
Programmable Logic Type
LOADABLE PLD
Package Equivalence Code
BGA324,18X18,40
Moisture Sensitivity Level
3
Number of Dedicated Inputs
4
Peak Reflow Temperature (Cel)
220
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
0
Time@Peak Reflow Temperature-Max (s)
20