DS1100LU-300+ by Analog Devices, Inc. | Sourcengine

Analog Devices, Inc. DS1100LU-300+

Lifecycle status
Active
RoHS
RoHS compliant
REACH
REACH compliant
Description
3-Volt 5-Tap Economy Timing Element (Delay Line)
Category
Semiconductors Logic ICs Delay Lines SILICON DELAY LINE

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
1100
Technology
CMOS
Width (mm)
3
Length (mm)
3
JESD-30 Code
S-PDSO-G8
Package Code
TSSOP
Logic IC Type
SILICON DELAY LINE
Package Shape
SQUARE
Package Style
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e3
Output Polarity
TRUE
Terminal Finish
Matte Tin (Sn) - annealed
DLA Qualification
Not Qualified
Temperature Grade
INDUSTRIAL
Terminal Position
DUAL
Number of Functions
1
Number of Terminals
8
Terminal Pitch (mm)
0.65
Number of Taps/Steps
5
Total Delay-Nom (ns)
300
Package Body Material
PLASTIC/EPOXY
Seated Height-Max (mm)
1.1
Supply Voltage-Max (V)
3.6
Supply Voltage-Min (V)
3
Supply Voltage-Nom (V)
3.3
Programmable Delay Line
NO
Supply Current-Max (mA)
10
Package Equivalence Code
TSSOP8,.19
Moisture Sensitivity Level
1
Output Impedance-Nom (ohm)
50
Peak Reflow Temperature (Cel)
260
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
-40
Propagation Delay-Max@Nom-Sup (ns)
300
Time@Peak Reflow Temperature-Max (s)
30