CS18HS10245TC-12 by Chiplus Semiconductor Corp. | Sourcengine

Chiplus Semiconductor Corp. CS18HS10245TC-12

Lifecycle status
Contact Mfr
Description
Application Specific SRAM, 128KX8, 12ns, CMOS, PDIP32
Category
Semiconductors Memory ICs SRAMs APPLICATION SPECIFIC SRAM

ECCN
3A991.b.2.b
ECCN Governance
EAR
HTS Code
8542.32.00.41
SB Code
8542.32.00.40

I/O Type
COMMON
Technology
CMOS
Width (mm)
7.62
Length (mm)
40.64
JESD-30 Code
R-PDIP-T32
Memory Width
8
Package Code
DIP
Package Shape
RECTANGULAR
Package Style
IN-LINE Meter
Surface Mount
NO
Terminal Form
THROUGH-HOLE
J-STD-609 Code
e0
Memory IC Type
APPLICATION SPECIFIC SRAM
Operating Mode
ASYNCHRONOUS
Parallel/Serial
PARALLEL
Terminal Finish
TIN LEAD
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
DUAL
Additional Feature
SEATED HT-CALCULATED
Memory Organization
128KX8
Number of Functions
1
Number of Terminals
32
Terminal Pitch (mm)
2.54
Access Time-Max (ns)
12
Number of Words Code
128K
Memory Density (bits)
1048576
Package Body Material
PLASTIC/EPOXY
Output Characteristics
3-STATE
Seated Height-Max (mm)
4.953
Supply Voltage-Max (V)
5.5
Supply Voltage-Min (V)
4.5
Supply Voltage-Nom (V)
5
Number of Words (words)
131072
Standby Current-Max (A)
0.005
Standby Voltage-Min (V)
4.5
Supply Current-Max (mA)
160
Package Equivalence Code
DIP32,.6
Moisture Sensitivity Level
3
Peak Reflow Temperature (Cel)
235
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0