CL3K-67132L-70
MATRA MHS
- Lifecycle statusDiscontinued
- DescriptionMulti-Port SRAM, 2KX8, 70ns, CMOS, PDIP48
- Category
- ECCNEAR99
- ECCN GovernanceEAR
- HTS Code8542.32.00.41
- SB Code8542.32.00.40
- TechnologyCMOS
- JESD-30 CodeR-PDIP-T48
- Memory Width8
- Package CodeDIP
- Output EnableYES
- Package ShapeRECTANGULAR
- Package StyleIN-LINE Meter
- Surface MountNO
- Terminal FormTHROUGH-HOLE
- Memory IC TypeMULTI-PORT SRAM
- Operating ModeASYNCHRONOUS
- Number of Ports2
- Parallel/SerialPARALLEL
- DLA QualificationNot Qualified
- Temperature GradeCOMMERCIAL
- Terminal PositionDUAL
- Additional FeatureARBITER
- Memory Organization2KX8
- Number of Functions1
- Number of Terminals48
- Access Time-Max (ns)70
- Number of Words Code2K
- Memory Density (bits)16384
- Package Body MaterialPLASTIC/EPOXY
- Output Characteristics3-STATE
- Supply Voltage-Max (V)3.6
- Supply Voltage-Min (V)3
- Supply Voltage-Nom (V)3.3
- Number of Words (words)2048
- Standby Voltage-Min (V)2
- Operating Temperature-Max (Cel)70
- Operating Temperature-Min (Cel)0
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