CDC3RL02YFPR by Texas Instruments Incorporated | Sourcengine

Texas Instruments Incorporated CDC3RL02YFPR

Lifecycle status
Active
RoHS
RoHS compliant
REACH
REACH compliant
Description
Dual-channel square/sine-to-square wave clock buffer 8-DSBGA -40 to 85
Category
Semiconductors UPs/uCs/Peripheral ICs Timers or RTCs

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.39.00.60
SB Code
8542.39.00.00

Family
CDC
Width (mm)
0.77
Length (mm)
1.57
JESD-30 Code
R-PBGA-B8
Package Code
VFBGA
Logic IC Type
LOW SKEW CLOCK DRIVER
Package Shape
RECTANGULAR
Package Style
GRID ARRAY, VERY THIN PROFILE, FINE PITCH Meter
Surface Mount
YES
Terminal Form
BALL
J-STD-609 Code
e1
Packing Method
TR
fmax-Min (MHz)
52.0000
Terminal Finish
Tin/Silver/Copper (Sn/Ag/Cu)
DLA Qualification
Not Qualified
Temperature Grade
INDUSTRIAL
Terminal Position
BOTTOM
Input Conditioning
STANDARD
Number of Functions
1
Number of Terminals
8
Terminal Pitch (mm)
0.4
Load Capacitance (pF)
50.0000
Package Body Material
PLASTIC/EPOXY
Number of True Outputs
2
Seated Height-Max (mm)
0.5
Supply Voltage-Max (V)
5.5
Supply Voltage-Min (V)
2.3
Supply Voltage-Nom (V)
1.8
Supply Current-Max (mA)
1
Package Equivalence Code
BGA8,2X4,16
Moisture Sensitivity Level
1
Number of Inverted Outputs
0
Output Low Current-Max (mA)
8.000000000000000
Peak Reflow Temperature (Cel)
260
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
-40
Same Edge Clock Skew Delay-Max (ns)
0.5
Time@Peak Reflow Temperature-Max (s)
30