9DBL1200AGLFT by Integrated Device Technology, Inc. | Sourcengine

Integrated Device Technology, Inc. 9DBL1200AGLFT

Lifecycle status
Discontinued
RoHS
RoHS compliant
REACH
REACH compliant
Description
PLL Based Clock Driver, 9DBL Series, 24 True Output(s), 0 Inverted Output(s), PDSO64
Category
Semiconductors Logic ICs Clock Drivers PLL BASED CLOCK DRIVER

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
9DBL
Width (mm)
6.1
Length (mm)
17
JESD-30 Code
R-PDSO-G64
Package Code
TSSOP
Logic IC Type
PLL BASED CLOCK DRIVER
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e3
Terminal Finish
Matte Tin (Sn)
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
DUAL
Input Conditioning
DIFFERENTIAL MUX
Number of Functions
1
Number of Terminals
64
Terminal Pitch (mm)
0.5
Package Body Material
PLASTIC/EPOXY
Number of True Outputs
24
Output Characteristics
3-STATE
Seated Height-Max (mm)
1.2
Supply Voltage-Max (V)
3.465
Supply Voltage-Min (V)
3.135
Supply Voltage-Nom (V)
3.3
Package Equivalence Code
TSSOP64,.32,20
Number of Inverted Outputs
0
Output Low Current-Max (mA)
250
Peak Reflow Temperature (Cel)
260
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0
Same Edge Clock Skew Delay-Max (ns)
0.05
Time@Peak Reflow Temperature-Max (s)
30