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74LVTH182512DGGRG4

Texas Instruments Incorporated

74LVTH182512DGGRG4 Datasheet
Texas Instruments Incorporated 74LVTH182512DGGRG4
  • ECCN
    EAR99
  • ECCN Governance
    EAR
  • HTS Code
    8542.39.00.90
  • SB Code
    8542.39.00.60
  • Family
    LVT
  • Direction
    BIDIRECTIONAL
  • Technology
    CMOS
  • Width (mm)
    6.1
  • Length (mm)
    17
  • Control Type
    INDEPENDENT CONTROL
  • JESD-30 Code
    R-PDSO-G64
  • Package Code
    TSSOP
  • Trigger Type
    POSITIVE EDGE
  • Logic IC Type
    BOUNDARY SCAN REG BUS TRANSCEIVER
  • Package Shape
    RECTANGULAR
  • Package Style
    SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
  • Surface Mount
    YES
  • Terminal Form
    GULL WING
  • J-STD-609 Code
    e4
  • Number of Bits
    9
  • Packing Method
    TR
  • Number of Ports
    2
  • Output Polarity
    TRUE
  • Terminal Finish
    Nickel/Palladium/Gold (Ni/Pd/Au)
  • DLA Qualification
    Not Qualified
  • Temperature Grade
    INDUSTRIAL
  • Terminal Position
    DUAL
  • Number of Functions
    18
  • Number of Terminals
    64
  • Terminal Pitch (mm)
    0.5
  • Load Capacitance (pF)
    50
  • Package Body Material
    PLASTIC/EPOXY
  • Output Characteristics
    3-STATE WITH SERIES RESISTOR
  • Propagation Delay (ns)
    7.7
  • Seated Height-Max (mm)
    1.2
  • Supply Voltage-Max (V)
    3.6
  • Supply Voltage-Min (V)
    2.7
  • Supply Voltage-Nom (V)
    3.3
  • Supply Current-Max (mA)
    24
  • Package Equivalence Code
    TSSOP64,.32,20
  • Moisture Sensitivity Level
    1
  • Output Low Current-Max (mA)
    32
  • Peak Reflow Temperature (Cel)
    260
  • Operating Temperature-Max (Cel)
    85
  • Operating Temperature-Min (Cel)
    -40
  • Propagation Delay-Max@Nom-Sup (ns)
    5.7
  • Time@Peak Reflow Temperature-Max (s)
    30

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74LVTH182512DGGRG4
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74LVTH182512DGGRG4