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72104L50P

Integrated Device Technology, Inc.

Integrated Device Technology, Inc. 72104L50P
  • ECCN
    EAR99
  • ECCN Governance
    EAR
  • HTS Code
    8542.32.00.71
  • SB Code
    8542.32.00.70
  • Technology
    CMOS
  • JESD-30 Code
    R-PDIP-T40
  • Memory Width
    9
  • Package Code
    DIP
  • Output Enable
    YES
  • Package Shape
    RECTANGULAR
  • Package Style
    IN-LINE Meter
  • Surface Mount
    NO
  • Terminal Form
    THROUGH-HOLE
  • J-STD-609 Code
    e0
  • Memory IC Type
    OTHER FIFO
  • Operating Mode
    ASYNCHRONOUS
  • Cycle Time (ns)
    65
  • Parallel/Serial
    PARALLEL
  • Terminal Finish
    TIN LEAD
  • DLA Qualification
    Not Qualified
  • Temperature Grade
    COMMERCIAL
  • Terminal Position
    DUAL
  • Memory Organization
    4KX9
  • Number of Functions
    1
  • Number of Terminals
    40
  • Terminal Pitch (mm)
    2.54
  • Access Time-Max (ns)
    50
  • Number of Words Code
    4K
  • Memory Density (bits)
    36864
  • Package Body Material
    PLASTIC/EPOXY
  • Supply Voltage-Nom (V)
    5
  • Number of Words (words)
    4096
  • Standby Current-Max (A)
    0.002
  • Supply Current-Max (mA)
    140
  • Package Equivalence Code
    DIP40,.6
  • Clock Frequency-Max (MHz)
    15
  • Moisture Sensitivity Level
    1
  • Peak Reflow Temperature (Cel)
    245
  • Operating Temperature-Max (Cel)
    70
  • Operating Temperature-Min (Cel)
    0

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72104L50P
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72104L50P