7133S55P by Integrated Device Technology, Inc. | Sourcengine

Integrated Device Technology, Inc. 7133S55P

Lifecycle status
Discontinued
Description
Multi-Port SRAM, 2KX16, 55ns, CMOS, PDIP68
Category
Semiconductors Memory ICs SRAMs MULTI-PORT SRAM

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.32.00.41
SB Code
8542.32.00.40

I/O Type
COMMON
Technology
CMOS
JESD-30 Code
R-PDIP-T68
Memory Width
16
Package Code
SDIP
Package Shape
RECTANGULAR
Package Style
IN-LINE, SHRINK PITCH Meter
Surface Mount
NO
Terminal Form
THROUGH-HOLE
J-STD-609 Code
e0
Memory IC Type
MULTI-PORT SRAM
Operating Mode
ASYNCHRONOUS
Number of Ports
2
Parallel/Serial
PARALLEL
Terminal Finish
TIN LEAD
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
DUAL
Memory Organization
2KX16
Number of Terminals
68
Terminal Pitch (mm)
1.78
Access Time-Max (ns)
55
Number of Words Code
2K
Memory Density (bits)
32768
Package Body Material
PLASTIC/EPOXY
Output Characteristics
3-STATE
Supply Voltage-Max (V)
5.5
Supply Voltage-Min (V)
4.5
Supply Voltage-Nom (V)
5
Number of Words (words)
2048
Standby Current-Max (A)
0.015
Standby Voltage-Min (V)
4.5
Supply Current-Max (mA)
210
Package Equivalence Code
SDIP68,.6
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0