71322S70J by Integrated Device Technology, Inc. | Sourcengine

Integrated Device Technology, Inc. 71322S70J

Lifecycle status
Transferred
REACH
REACH compliant
Description
PLCC 19.00x19.00x3.63 mm 1.27mm Pitch
Category
Semiconductors Memory ICs SRAMs MULTI-PORT SRAM

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.32.00.41
SB Code
8542.32.00.40

Technology
CMOS
JESD-30 Code
S-PQCC-J52
Memory Width
8
Organization
2KX8
Package Code
QCCJ
JESD-609 Code
e0
Package Shape
SQUARE
Package Style
CHIP CARRIER Meter
Surface Mount
YES
Terminal Form
J BEND
Memory Density
16384 bit
Memory IC Type
MULTI-PORT SRAM
Operating Mode
ASYNCHRONOUS
Terminal Pitch
1.27 mm
Access Time-Max
70 ns
Number of Ports
2
Number of Words
2048 words
Parallel/Serial
PARALLEL
Terminal Finish
TIN LEAD
Temperature Grade
COMMERCIAL
Terminal Position
QUAD
Number of Functions
1
Number of Terminals
52
Standby Current-Max
0.015 Amp
Standby Voltage-Min
4.5 V
Number of Words Code
2K
Qualification Status
Not Qualified
Package Body Material
PLASTIC/EPOXY
Output Characteristics
3-STATE
Package Equivalence Code
LDCC52,.8SQ
Operating Temperature-Max
70 Cel
Operating Temperature-Min
0 Cel
Supply Voltage-Max (Vsup)
5.5 V
Supply Voltage-Min (Vsup)
4.5 V
Supply Voltage-Nom (Vsup)
5 V
Moisture Sensitivity Level
1
Peak Reflow Temperature (Cel)
225
Time@Peak Reflow Temperature-Max (s)
20