7012L20C by Integrated Device Technology, Inc. | Sourcengine

Integrated Device Technology, Inc. 7012L20C

Lifecycle status
Discontinued
Description
Multi-Port SRAM, 2KX9, 20ns, CMOS, CDIP48
Category
Semiconductors Memory ICs SRAMs MULTI-PORT SRAM

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.32.00.41
SB Code
8542.32.00.40

I/O Type
COMMON
Technology
CMOS
Width (mm)
15.24
Length (mm)
60.96
JESD-30 Code
R-CDIP-T48
Memory Width
9
Package Code
SDIP
Package Shape
RECTANGULAR
Package Style
IN-LINE, SHRINK PITCH Meter
Surface Mount
NO
Terminal Form
THROUGH-HOLE
J-STD-609 Code
e0
Memory IC Type
MULTI-PORT SRAM
Operating Mode
ASYNCHRONOUS
Number of Ports
2
Parallel/Serial
PARALLEL
Terminal Finish
TIN LEAD
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
DUAL
Memory Organization
2KX9
Number of Terminals
48
Terminal Pitch (mm)
2.54
Access Time-Max (ns)
20
Number of Words Code
2K
Memory Density (bits)
18432
Package Body Material
CERAMIC, METAL-SEALED COFIRED
Output Characteristics
3-STATE
Seated Height-Max (mm)
4.826
Supply Voltage-Max (V)
5.5
Supply Voltage-Min (V)
4.5
Supply Voltage-Nom (V)
5
Number of Words (words)
2048
Package Equivalence Code
DIP48,.6
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0