54F68AQMX by NATIONAL SEMICONDUCTOR CORP | Sourcengine

NATIONAL SEMICONDUCTOR CORP 54F68AQMX

Lifecycle status
Discontinued
Description
DRAM Controller, 256K X 1, Bipolar, PQCC52
Category
Semiconductors UPs/uCs/Peripheral ICs Memory Controllers MEMORY CONTROLLER, DRAM

ECCN
3A001.a.2.c
ECCN Governance
EAR
HTS Code
8542.31.00.30
SB Code
8542.31.00.30

Technology
BIPOLAR
Width (mm)
19.05
Length (mm)
19.05
JESD-30 Code
S-PQCC-J52
Package Code
QCCJ
Boundary Scan
NO
Package Shape
SQUARE
Package Style
CHIP CARRIER Meter
Surface Mount
YES
Terminal Form
J BEND
Low Power Mode
NO
Number of Banks
4
Address Bus Width
20
DLA Qualification
Not Qualified
Temperature Grade
MILITARY
Terminal Position
QUAD
Memory Organization
256K X 1
Number of Terminals
52
Terminal Pitch (mm)
1.27
Package Body Material
PLASTIC/EPOXY
Seated Height-Max (mm)
4.57
Supply Voltage-Max (V)
5.5
Supply Voltage-Min (V)
4.5
Supply Voltage-Nom (V)
5
External Data Bus Width
0
Supply Current-Max (mA)
300
uPs/uCs/Peripheral ICs Type
MEMORY CONTROLLER, DRAM
Operating Temperature-Max (Cel)
125
Operating Temperature-Min (Cel)
-55