100118F
PHILIPS SEMICONDUCTORS
- Lifecycle statusDiscontinued
- DescriptionOR-AND/OR-AND-Invert Gate, ECL, CDIP24
- Category
- HTS Code8542.39.00.01
- SB Code8542.39.00.00
- TechnologyECL
- JESD-30 CodeR-XDIP-T24
- Package CodeDIP
- Logic IC TypeOR-AND/OR-AND-INVERT GATE
- Package ShapeRECTANGULAR
- Package StyleIN-LINE Meter
- Surface MountNO
- Terminal FormTHROUGH-HOLE
- J-STD-609 Codee0
- Schmitt TriggerNO
- Terminal FinishTin/Lead (Sn/Pb)
- DLA QualificationNot Qualified
- Temperature GradeOTHER
- Terminal PositionDUAL
- Number of Terminals24
- Terminal Pitch (mm)2.54
- Package Body MaterialCERAMIC
- Supply Current-Max (mA)92
- Package Equivalence CodeDIP24,.4
- Operating Temperature-Max (Cel)85
- Operating Temperature-Min (Cel)0
- Propagation Delay-Max@Nom-Sup (ns)3.4
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100118F