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ZPSD512B1-70LM

WAFERSCALE INTEGRATION INC

WAFERSCALE INTEGRATION INC ZPSD512B1-70LM
  • ECCN
    3A001.a.2.c
  • ECCN Governance
    EAR
  • HTS Code
    8542.31.00.55
  • SB Code
    8542.31.00.55
  • JTAG BST
    NO
  • Technology
    CMOS
  • Width (mm)
    24.105
  • Length (mm)
    24.105
  • Architecture
    PAL-TYPE
  • JESD-30 Code
    S-CQCC-J68
  • Organization
    0 DEDICATED INPUTS, 40 I/O
  • Package Code
    WQCCJ
  • Package Shape
    SQUARE
  • Package Style
    CHIP CARRIER, WINDOW Meter
  • Surface Mount
    YES
  • Terminal Form
    J BEND
  • Output Function
    MACROCELL
  • Number of Inputs
    40
  • Number of Outputs
    40
  • Terminal Position
    QUAD
  • Number of I/O Lines
    40
  • Number of Terminals
    68
  • Terminal Pitch (mm)
    1.27
  • Number of Macro Cells
    30
  • Package Body Material
    CERAMIC, METAL-SEALED COFIRED
  • In-System Programmable
    NO
  • Propagation Delay (ns)
    27
  • Seated Height-Max (mm)
    4.57
  • Supply Voltage-Max (V)
    5.5
  • Supply Voltage-Min (V)
    4.5
  • Supply Voltage-Nom (V)
    5
  • Number of Product Terms
    140
  • Programmable Logic Type
    UV PLD
  • Package Equivalence Code
    LDCC68,1.0SQ
  • Clock Frequency-Max (MHz)
    30.3
  • Number of Dedicated Inputs
    0
  • Operating Temperature-Max (Cel)
    125
  • Operating Temperature-Min (Cel)
    -55

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ZPSD512B1-70LM
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ZPSD512B1-70LM