XC9572XL-7VQ64I by Xilinx,Inc. | Sourcengine

Xilinx,Inc. XC9572XL-7VQ64I

Lifecycle status
Transferred
Description
CPLD XC9500XL Family 1.6K Gates 72 Macro Cells 125MHz 0.35um (CMOS) Technology 3.3V 64-Pin VTQFP
Category
Semiconductors Programmable Logic ICs Programmable Logic Devices FLASH PLD

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.39.00.01
SB Code
8542.39.00.00

JTAG BST
YES
Technology
CMOS
Width (mm)
10
Length (mm)
10
JESD-30 Code
S-PQFP-G64
Organization
0 DEDICATED INPUTS, 52 I/O
Package Code
TFQFP
Package Shape
SQUARE
Package Style
FLATPACK, THIN PROFILE, FINE PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
Number of Inputs
36
DLA Qualification
Not Qualified
Number of Outputs
36
Temperature Grade
INDUSTRIAL
Terminal Position
QUAD
Additional Feature
72 MACROCELLS
Number of I/O Lines
52
Number of Terminals
64
Terminal Pitch (mm)
0.5
Number of Macro Cells
72
Package Body Material
PLASTIC/EPOXY
In-System Programmable
YES
Propagation Delay (ns)
7.5
Seated Height-Max (mm)
1.2
Supply Voltage-Max (V)
3.6
Supply Voltage-Min (V)
3
Supply Voltage-Nom (V)
3.3
Programmable Logic Type
FLASH PLD
Package Equivalence Code
TQFP64,.47SQ
Clock Frequency-Max (MHz)
125
Moisture Sensitivity Level
3
Number of Dedicated Inputs
0
Peak Reflow Temperature (Cel)
240
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
-40
Time@Peak Reflow Temperature-Max (s)
30