SN74LVC112APWT by Texas Instruments Incorporated | Sourcengine

Texas Instruments Incorporated SN74LVC112APWT

Lifecycle status
Active
RoHS
RoHS compliant
REACH
REACH compliant
Description
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-TSSOP -40 to 125
Category
Semiconductors Logic ICs FF/Latches

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
LVC/LCX/Z
Technology
CMOS
Width (mm)
4.4
Length (mm)
5
JESD-30 Code
R-PDSO-G16
Package Code
TSSOP
Trigger Type
NEGATIVE EDGE
Logic IC Type
J-K FLIP-FLOP
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e4
Number of Bits
2
Packing Method
TR
fmax-Min (MHz)
150
Output Polarity
COMPLEMENTARY
Schmitt Trigger
NO
Terminal Finish
Nickel/Palladium/Gold (Ni/Pd/Au)
DLA Qualification
Not Qualified
Temperature Grade
AUTOMOTIVE
Terminal Position
DUAL
Number of Functions
2
Number of Terminals
16
Terminal Pitch (mm)
0.65
Load Capacitance (pF)
50
Package Body Material
PLASTIC/EPOXY
Propagation Delay (ns)
7.1
Seated Height-Max (mm)
1.2
Supply Voltage-Max (V)
3.6
Supply Voltage-Min (V)
2
Supply Voltage-Nom (V)
1.8
Supply Current-Max (mA)
0.01
Package Equivalence Code
TSSOP16,.25
Frequency-Max@Nom-Sup (Hz)
150000000
Moisture Sensitivity Level
1
Output Low Current-Max (mA)
24
Peak Reflow Temperature (Cel)
260
Operating Temperature-Max (Cel)
125
Operating Temperature-Min (Cel)
-40
Propagation Delay-Max@Nom-Sup (ns)
4.8
Time@Peak Reflow Temperature-Max (s)
NOT SPECIFIED
Number of Elements
2