SN74LVC112ADR
Texas Instruments Incorporated
- Lifecycle statusActive
- RoHSRoHS compliant
- REACHREACH compliant
- DescriptionDual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SOIC -40 to 125
- Category
- ECCNEAR99
- ECCN GovernanceEAR
- HTS Code8542.39.00.01
- SB Code8542.39.00.00
- FamilyLVC/LCX/Z
- TechnologyCMOS
- Width (mm)3.9
- Length (mm)9.9
- JESD-30 CodeR-PDSO-G16
- Package CodeSOP
- Trigger TypeNEGATIVE EDGE
- Logic IC TypeJ-K FLIP-FLOP
- Package ShapeRECTANGULAR
- Package StyleSMALL OUTLINE Meter
- Surface MountYES
- Terminal FormGULL WING
- J-STD-609 Codee4
- Number of Bits2
- Packing MethodTR
- fmax-Min (MHz)150
- Output PolarityCOMPLEMENTARY
- Schmitt TriggerNO
- Terminal FinishNickel/Palladium/Gold (Ni/Pd/Au)
- DLA QualificationNot Qualified
- Temperature GradeAUTOMOTIVE
- Terminal PositionDUAL
- Number of Functions2
- Number of Terminals16
- Terminal Pitch (mm)1.27
- Load Capacitance (pF)50
- Package Body MaterialPLASTIC/EPOXY
- Propagation Delay (ns)7.1
- Seated Height-Max (mm)1.75
- Supply Voltage-Max (V)3.6
- Supply Voltage-Min (V)2
- Supply Voltage-Nom (V)1.8
- Supply Current-Max (mA)0.01
- Package Equivalence CodeSOP16,.25
- Frequency-Max@Nom-Sup (Hz)150000000
- Moisture Sensitivity Level1
- Output Low Current-Max (mA)24
- Peak Reflow Temperature (Cel)260
- Operating Temperature-Max (Cel)125
- Operating Temperature-Min (Cel)-40
- Propagation Delay-Max@Nom-Sup (ns)4.8
- Time@Peak Reflow Temperature-Max (s)NOT SPECIFIED
- Number of Elements2
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SN74LVC112ADR