SN74LV10APWR by Texas Instruments Incorporated | Sourcengine

Texas Instruments Incorporated SN74LV10APWR

Lifecycle status
Active
RoHS
RoHS compliant
REACH
REACH compliant
Description
3-ch, 3-input, 2-V to 5.5-V NAND gates 14-TSSOP -40 to 85
Category
Semiconductors Logic ICs Gates

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
LV/LV-A/LVX/H
Technology
CMOS
Width (mm)
4.4
Length (mm)
5
JESD-30 Code
R-PDSO-G14
Package Code
TSSOP
Logic IC Type
NAND GATE
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e4
Packing Method
TR
Schmitt Trigger
NO
Terminal Finish
Nickel/Palladium/Gold (Ni/Pd/Au)
Number of Inputs
3
DLA Qualification
Not Qualified
Temperature Grade
INDUSTRIAL
Terminal Position
DUAL
Number of Functions
3
Number of Terminals
14
Terminal Pitch (mm)
0.65
Load Capacitance (pF)
50
Package Body Material
PLASTIC/EPOXY
Propagation Delay (ns)
20.5
Seated Height-Max (mm)
1.2
Supply Voltage-Max (V)
5.5
Supply Voltage-Min (V)
2
Supply Voltage-Nom (V)
2.5
Supply Current-Max (mA)
0.02
Package Equivalence Code
TSSOP14,.25
Moisture Sensitivity Level
1
Output Low Current-Max (mA)
12
Peak Reflow Temperature (Cel)
260
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
-40
Propagation Delay-Max@Nom-Sup (ns)
13.5
Time@Peak Reflow Temperature-Max (s)
NOT SPECIFIED