PLSI2064-80LJ by Lattice Semiconductor | Sourcengine

Lattice Semiconductor PLSI2064-80LJ

Lifecycle status
Discontinued
Description
EE PLD, 18.5ns, 64-Cell, CMOS, PQCC84
Category
Semiconductors Programmable Logic ICs Programmable Logic Devices EE PLD

HTS Code
8542.39.00.01
SB Code
8542.31.00.55

JTAG BST
NO
Technology
CMOS
Width (mm)
29.3116
Length (mm)
29.3116
JESD-30 Code
S-PQCC-J84
Organization
4 DEDICATED INPUTS, 64 I/O
Package Code
QCCJ
Package Shape
SQUARE
Package Style
CHIP CARRIER Meter
Surface Mount
YES
Terminal Form
J BEND
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
QUAD
Additional Feature
3 EXTERNAL CLOCKS
Number of I/O Lines
64
Number of Terminals
84
Terminal Pitch (mm)
1.27
Number of Macro Cells
64
Package Body Material
PLASTIC/EPOXY
In-System Programmable
NO
Propagation Delay (ns)
18.5
Seated Height-Max (mm)
4.57
Supply Voltage-Max (V)
5.25
Supply Voltage-Min (V)
4.75
Supply Voltage-Nom (V)
5
Programmable Logic Type
EE PLD
Package Equivalence Code
LDCC84,1.2SQ
Clock Frequency-Max (MHz)
57
Moisture Sensitivity Level
3
Number of Dedicated Inputs
4
Peak Reflow Temperature (Cel)
225
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0
Time@Peak Reflow Temperature-Max (s)
30