CDCVF857DGGR by Texas Instruments Incorporated | Sourcengine

Texas Instruments Incorporated CDCVF857DGGR

Lifecycle status
Active
RoHS
RoHS compliant
REACH
REACH compliant
Description
2.5-V phase lock loop DDR clock driver 48-TSSOP -40 to 85
Category
Semiconductors UPs/uCs/Peripheral ICs Clock Generators

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
857
Width (mm)
6.1
Length (mm)
12.5
JESD-30 Code
R-PDSO-G48
Package Code
TSSOP
Logic IC Type
PLL BASED CLOCK DRIVER
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e4
Packing Method
TR
fmax-Min (MHz)
220
Terminal Finish
NICKEL PALLADIUM GOLD
DLA Qualification
Not Qualified
Temperature Grade
INDUSTRIAL
Terminal Position
DUAL
Input Conditioning
DIFFERENTIAL
Number of Functions
1
Number of Terminals
48
Terminal Pitch (mm)
0.5
Load Capacitance (pF)
14
Package Body Material
PLASTIC/EPOXY
Number of True Outputs
10
Output Characteristics
3-STATE
Propagation Delay (ns)
3.5
Seated Height-Max (mm)
1.2
Supply Voltage-Max (V)
2.7
Supply Voltage-Min (V)
2.3
Supply Voltage-Nom (V)
2.5
Supply Current-Max (mA)
10
Package Equivalence Code
TSSOP48,.3,20
Moisture Sensitivity Level
2
Number of Inverted Outputs
0
Output Low Current-Max (mA)
12
Peak Reflow Temperature (Cel)
260
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
-40
Same Edge Clock Skew Delay-Max (ns)
.04
Time@Peak Reflow Temperature-Max (s)
30