AS5C1008DJECJ-20XT by AUSTIN SEMICONDUCTOR INC | Sourcengine

AUSTIN SEMICONDUCTOR INC AS5C1008DJECJ-20XT

Lifecycle status
Transferred
Description
Cache SRAM, 128KX8, 20ns, CMOS, CDSO32
Category
Semiconductors Memory ICs SRAMs CACHE SRAM

ECCN
3A991.b.2.b
ECCN Governance
EAR
HTS Code
8542.32.00.41
SB Code
8542.32.00.40

Technology
CMOS
Width (mm)
10.2
Length (mm)
21
JESD-30 Code
R-CDSO-J32
Memory Width
8
Package Code
SOJ
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE Meter
Surface Mount
YES
Terminal Form
J BEND
J-STD-609 Code
e0
Memory IC Type
CACHE SRAM
Operating Mode
ASYNCHRONOUS
Parallel/Serial
PARALLEL
Terminal Finish
TIN LEAD
DLA Qualification
Not Qualified
Temperature Grade
MILITARY
Terminal Position
DUAL
Additional Feature
LOW POWER STANDBY MODE
Memory Organization
128KX8
Number of Functions
1
Number of Terminals
32
Terminal Pitch (mm)
1.27
Access Time-Max (ns)
20
Number of Words Code
128K
Memory Density (bits)
1048576
Package Body Material
CERAMIC, METAL-SEALED COFIRED
Seated Height-Max (mm)
3.7
Supply Voltage-Max (V)
5.5
Supply Voltage-Min (V)
4.5
Supply Voltage-Nom (V)
5
Number of Words (words)
131072
Operating Temperature-Max (Cel)
125
Operating Temperature-Min (Cel)
-55